Portfile

# $Id: Portfile 22478 2007-03-02 05:16:40Z pipping@macports.org $

PortSystem 1.0
name iverilog
version 0.8.2
categories science
maintainers nomaintainer@macports.org
description Icarus Verilog
long_description \
Icarus Verilog is a Verilog simulation and synthesis tool. It \
operates as a compiler, compiling source code writen in Verilog \
(IEEE-1364) into some target format. For batch simulation, the \
compiler can generate C++ code that is compiled and linked with \
a run time library (called \"vvm\") then executed as a command to \
run the simulation. For synthesis, the compiler generates netlists \
in the desired format.
homepage http://www.icarus.com/eda/verilog/
platforms darwin

master_sites ftp://ftp.icarus.com/pub/eda/verilog/v0.8/
distname verilog-${version}
checksums md5 41650504e4460508a0800008a2628e07

configure.args mandir=\\\${prefix}/share/man
destroot.destdir prefix=${destroot}${prefix}

test.run yes
test.target check

files