Portfile

# $Id: Portfile 22478 2007-03-02 05:16:40Z pipping@macports.org $

PortSystem 1.0
name vbs
version 1.4.0
categories science
maintainers nomaintainer@macports.org
description Verilog Behavioral Simulator
long_description \
This is the public release of the Verilog Behavioral Simulator. \
Verilog is a Hardware Description Language used mostly for digital \
circuit design and simulation. This program is a simple \
implementation of a Verilog simulator. VBS tries to implement all \
of the Verilog behavioral constructs that are synthesizable, but \
still allow complex test vectors for simulation.
homepage http://www.flex.com/~jching/
platforms darwin
master_sites ${homepage}
checksums md5 07619d3dbfc030639d8ed1271f792d62
worksrcdir ${distname}/src

patchfiles patch-Makefile.in
configure.args --disable-debug
build.target ${name}
test.run yes
test.target test-all testv-all
destroot.destdir prefix=${destroot}${prefix}

files